The present invention relates to a communication control circuit for transmission and reception of data, and in particular, to an interface control LSI apparatus for an industrial measurement communication network "field bus".
FIGS. 9 and 10 show an outline of a communication apparatus using a conventional field bus.
In a communication system using a field bus as shown in FIG. 9, each of measurement and control equipments 911, 912, 913 with communication stations to which measurement blocks 908, such as programmable controller, pressure transmitter or flow transmitter, are attached, is connected to a pair of transmission paths 904 to mutual transmission and reception.
A communication block 907 in the measurement and control equipment with a communication station 911 comprises a bus interface circuit 903 connected to a transmission path 904, an interface control circuit or a modem circuit 901, and a host processor or a microcontroller 902 for controlling the interface control circuit 901.
The microcontroller 902 reads the measured values, manipulates actuators, and displays/instructs to external input/output devices relative to the measurement and control block 908.
The microcontroller 902 writes and reads transmit and receive data to and from the interface control circuit 901. During transmission, the interface control circuit 901 outputs TxD and a driver circuit 905 sends this signal out to the transmission path 904.
During reception, a receiver 906 outputs the signal on the transmission path 904 to the interface control circuit 901 as RxD.
When a signal is present on the transmission path 904, the receiver 906 outputs a CD signal to the interface control circuit 901.
FIG. 10 shows a detailed block diagram of the interface control circuit 901.
The microcontroller 902 writes transmit byte (8 bits) data to a transmit FIFO (First In First Out) 1006 in the interface control circuit 901 via a CPU interface 1017.
The interface control circuit 901 monitors the state of the transmission path 904 via a bus interface circuit 903 using the CD signal, and if no other communication station, e.g. 912 and 913, is sending a transmission, a transmission may be initiated.
A series of transmission operations is performed by a transmit state machine 1022 built in the interface control circuit 901, while the microcontroller 902 writes transmit data to a transmit FIFO 1006.
The interface control circuit 901 converts 8-bit byte data (parallel data) into serial data (1018), and adds a preamble and a start delimiter to the beginning of the data as well as 16-bit CRC and an end delimiter to the end of the data in order to form a transmit frame (1020).
These specially added codes are used at the receiver to match the length of one bit, detect the first and last byte positions of the frame, and check the presence of an error.
FIG. 11 shows the structure of a frame. The start and end delimiters include a special code to be differentiated from other components, but the preamble, data and CRC are formed of logical values 1 and 0.
The frame to be transmitted is encoded into Manchester codes (1021), which are then converted into voltage waveforms on the transmission path 904 by the driver circuit 905 in the bus interface circuit 903.
The control equipment with a communication station 911 and the other control equipments with communication stations 912 and 913 normally wait for a reception. When one communication station starts transmission, the voltage waveform on the transmission path 904 is converted into a digital signal (RxD) by the receiver circuit 906 in the bus interface circuit 903, and this digital signal (RxD) is received by the interface control circuit 901.
In FIG. 10, a series of reception operations is performed by a receive-state machine 1005. The received signal is Manchester-decoded (1010); the preamble and the start and end delimiters are removed (1015); and the CRC code is checked for errors (1013).
The serial data is sequentially converted into 8-bit byte data (1011), which is then stored in a receive FIFO 1007.
Once a specified number of bytes of the receive data has been accumulated in the FIFO 1007, an interrupt generator (1024) generates an interrupt signal (INT) to the microcontroller 902 to inform it of the presence of the receive data, and the microcontroller 902 reads the data from the receive FIFO 1007.
Since there are other causes for the generation of the interrupt signal (INT), an interrupt cause status register 1008 indicating a cause of generation of the interrupt signal (INT) is provided to allow the microcontroller 902 to read this register to find the cause of the interruption.
Only the data portion of the receive frame is stored in the receive FIFO 1007, and the CRC code is not written to the FIFO 1007 except in special cases.
After detecting the presence of the receive data, the microcontroller 902 reads the data from the receive FIFO 1007. FIG. 12 shows the main timings for a receiving operation.
The writing to the receive FIFO 1007 is carried out 2 bytes after the data is loaded because the 2-byte CRC code following the data is not written to the FIFO 1007. The modem circuit does not know the length of the data beforehand, so it can not identify the boundary between the data and the CRC code.
Thus, a 16-bit shift register 1012 is provided between a Manchester decoding circuit 1010 and a serial/parallel conversion circuit 1011, so that the first byte of data is written to the receive FIFO 1007 after the third byte of data has been received, and the writing to the FIFO is completed when the end delimiter is detected. Consequently, when the end delimiter is detected, the two bytes preceding the end delimiter are determined to be a CRC code to prevent it from being written to the FIFO.
As shown in FIG. 12, if it is assumed that a threshold for the receive FIFO 1007 is 2 bytes and that the interrupt signal is generated when 2 bytes of data have been accumulated therein, an interruption occurs after the reception of the fourth byte of data, and the microcontroller 902 subsequently notes the presence of the receive data.
Data to be transmitted is not necessarily required by all the stations that are receiving the data.
Even if the communication station does not require the received data, the microcontroller 902 reads the received data to determine whether it is unnecessary, and if so, it outputs a reception stop instruction via a control register 1009 in order to suspend the receiving operation.
FIG. 13 shows a flow chart describing a receiving operation and the stoppage of the reception of the unnecessary data. Namely, data is transferred to FIFO from a condition of "wait for reception" through the operations of "detect received signal", "detect bit synchronization" and "detect byte synchronization".
When the number of data in FIFO comes to a predetermined threshold value, interruption occurs, so that the host processor knows the presence of the data in FIFO. As a result, the host processor reads the data in FIFO and determines if the data is required in the station. If the data is unwanted, the host processor outputs a stop reception signal through the control register 1009 and suspends the data reception operation. If the data is wanted, the reception of the data is continued.
After the reception has been stopped, the reception stop state is maintained until the receive frame has been finished. Once the receive frame has disappeared, the station returns to a reception wait state.
According to the conventional communication apparatuses, all the stations other than a transmitting station which are ready for reception receive data irrespective of whether the data is unwanted, and the host processor reads the receiving data accumulated in the receive FIFO to determine whether the read data is unwanted.
Thus, whenever other stations carry out transmissions, the host processor is activated and consumes power.
In addition, a certain amount of time must pass before the reception stop instruction is issued by the host processor. The example shown in FIG. 12 can not stop the reception before 4 bytes of data portion of the receive frame are received.
This invention has been made in view of the above points, and its object is to maintain the host processor in a sleep mode until the required receive frame has reached the communication station in order to reduce the power consumed by the communication apparatus.